Hybrid Monolithic 3-D IC Floorplanner

Monolithic and Hybrid Approaches

Thermal Solutions for 3-D IC, Packages and System

analysis model using current technology, as the model size could be excessively large. An accurate coanalysis fl ow methodology [6] is proposed to help manage thermal problems in 3-D ICs for chips in package on board confi gurations using a submodeling approach. Chip models at micron level serve as the submodel of a package/board model in mm scale, through a work fl ow for chip and package tool...

IP - SOC 2011 3 D IC 2 - tier 16 PE Multiprocessor with 3 D NoC Architecture Based on Tezzaron Technology

In this paper, we describe the design flow, architecture and implementation of our 3D multiprocessor with NoC. The design based on 16 processors communicating using a 4x2x2 mesh NoC spread on two tiers is discussed in detail and will be fabricated using Tezzaron technology with 130 nm Global Foundaries low power standard library. The purpose of this work is to accurately measure NoC performance...

A Monolithic Shape Memory Alloy Microgripper for 3-D Assembly of Tissue Engineering Scaffolds

This paper describes a microgripper used for the micro-assembly of an artificial scaffold for tissue engineering. The porous sponge-like scaffold is a three dimensional construct built by tiny unit parts of biodegradable polymer. This application requires the assembly of several parts by applying a suitable level of force. In this framework, a monolithic shape memory alloy (SMA) microgripper wa...

Nostradamus: a floorplanner of uncertain designs

Floorplanning is an early phase in chip planning. It provides information on approximate area, delay, power, and other performance measures. Careful floorplanning is thus of extreme importance. In many applications while a good floorplan is needed, not all modules’ information are available, or even worse, part of the provided information is inaccurate. Floorplanning with uncertainty is the pro...